Senior Staff CAD Engineer
About the job:
The Senior IC EDA/CAD Engineer will own and enhance the company’s EDA design environment,
signoff methodologies, and CAD infrastructure to enable successful first-pass silicon across
advanced semiconductor products.
We’re looking for someone who:
● Holds a bachelor’s or master’s degree in Electrical Engineering, Computer Engineering,
Computer Science, or a related field
● Has 5+ years of hands-on IC CAD engineering experience
● Has direct experience supporting advanced FinFET technologies (5nm, 3nm, or 2nm)
● Demonstrates deep expertise with Siemens Calibre (DRC, LVS, and PERC), Synopsys
StarRC, and Cadence Virtuoso and Innovus
● Is highly proficient in SKILL and Perl scripting, with working knowledge of Python, Tcl, and
Bash/Shell
● Has strong experience with Linux environments, compute cluster/grid management (such
as LSF or SGE), and version control systems such as Perforce or ICManage
● Excels at troubleshooting complex technical issues and improving engineering workflows
● Communicates effectively and collaborates well with cross-functional engineering teams
● Has experience with advanced node design challenges including multi-patterning,
layout-dependent effects (LDE), dummy fill, and DFM signoff (preferred)
● Has a background in custom layout or circuit design
● Is familiar with foundry engagement processes, including design rule waivers, PDK issue
reporting, and process qualification cycles (preferred)
● Demonstrates a proactive approach to problem-solving and continuous improvement
What you’ll do:
● Own and maintain the company’s EDA design environment, CAD infrastructure, and signoff
methodologies
● Install, qualify, and maintain advanced foundry PDKs for leading-edge FinFET technologies
● Manage compute infrastructure, license utilization, and engineering grid resources
● Develop, optimize, and support Cadence analog, mixed-signal, and digital implementation
flows
● Build and maintain physical verification and signoff flows using Siemens Calibre and
Synopsys StarRC
● Deploy and support EMIR simulation and PERC verification flows for advanced reliability
analysis
● Create automation scripts and utilities that improve efficiency and standardize engineering
workflows
● Troubleshoot EDA tool issues and serve as the primary technical interface with EDA
vendors
● Support RF, Analog, High-Speed IO, and Digital SoC development teams throughout the
design cycle
● Continuously improve CAD methodologies to enable reliable, first-time-right silicon
Why you’ll love working here:
● Weekly pay
● Paid sick leave
● Health, vision, dental, pet insurance, and more